With an improvement of processing capability of a communication apparatus and an information processing apparatus, an operating frequency of an LSI (Large Scale Integrated circuit) mounted on the apparatus increases and so does the frequency of noise components going round into a power feeding line. Commonly used decoupling technology is incapable of suppressing noise of approximately 10 MHz and less.
FIG. 1 is a diagram for explaining an example (prototype) of a decoupling technology in a power feeding line (also termed as feed line or power feed line). In the example shown in FIG. 1, an OBP (On Board Power-supply) 101 on a printed circuit board 100 supplies power to a plurality of LSIs (Large Scale Integrated Circuit) 103 via a common power feeding line 102. Low frequency decoupling capacitors 104 are provided a little away from the LSIs 103. High frequency decoupling capacitors 105 are provided neighboring to each LSI 103. In general, a decoupling capacitor (also known as “bypass capacitor”) is used to suppress power supply noise and EMI (Electro Magnetic Interference) generated from an electronic device. A decoupling capacitor is connected between a power supply and a ground (GND) of a power feeding line to reduce an impedance of a power supply line for a high frequency.
A ceramic capacitor (laminated ceramic chip capacitor) or the like is used as the high frequency decoupling capacitor 105. The high frequency decoupling capacitor 105 is provided neighboring to a high frequency circuit in order to reduce a path impedance to the high frequency circuit. The low frequency decoupling capacitor 104 is normally provided for each board.
In the example of the power feeding line shown in FIG. 1, a power supply solid layer (power supply plane) or a ground (GND) solid layer (ground plane) is provided over the entire surface of a board plane. Assuming that vertical and horizontal dimensions of the rectangular shaped printed circuit board 100 are B and A, respectively, a board area is Sb=A×B, and a maximum power feeding area is S=A×B.
FIG. 2 shows a decoupling effect. An abscissa and an ordinate indicate frequency and impedance, respectively. A power feeding line (board) stand-alone characteristic, a capacitor stand-alone characteristic, and the characteristic (impedance) when the capacitor is installed on the power feeding line are plotted. The characteristics in FIG. 2 indicate that the decoupling capacitor reduces the power feeding line impedance and contributes to the noise absorption. The capacitor installed has a self resonant frequency (a resonant frequency shown in the “capacitor stand-alone characteristic” in FIG. 2) lower than the self resonant frequency of the board alone.
Further, the capacitor is treated as an LCR series resonance circuit having parasitic components such as ESP (Equivalent Series Resistance) and ESL (Equivalent Series Inductance), and its impedance Z is given byZ=R+jωL+(1÷(jωC)), and
the resonant frequency f is given byf=1÷{2π√{square root over ( )}(LC)}
where R is a resistance (ESR),
L is an inductance (ESL),
C is a capacitance,
ω=2πf, and
j^2=−1 (^ is an exponential operator).
The characteristics (an abscissa: frequency, an ordinate: impedance) shown in FIG. 3 are plots when a self resonant frequency of a capacitor is higher than a self resonant frequency of a board alone. The graph indicates that no decoupling effect is obtained even in a frequency domain where a capacitor stand-alone characteristic exhibits lower impedance than the board stand-alone characteristic. The “capacitor+board characteristic,” the characteristic when the decoupling capacitor is mounted on the board, are the same as the “board stand-alone characteristic” (i.e., no decoupling effect).
A line speed of a communication apparatus in recent years has increased, and a processing speed of an apparatus processing line data such as a server, a PC (Personal Computer) continues to increase. For instance, a signal speed between a CPU (Central Processing Unit) and a memory is nearly 1 GHz (Giga Hertz), and noise components going round into a power feeding line have been made to a high frequency. This causes a problem that decoupling cannot be achieved.
For instance, the following literatures regarding the decoupling technology are known, but none solves the problem above.
Patent Literature 1 discloses a circuit designing method capable of disposing a bypass capacitor having an optimum capacitance value at an optimum location and reducing noise accompanying power supply voltage variation, while verifying effects in detail by first temporarily setting a capacitance of a bypass capacitor and a location thereof; then processing an impedance-frequency characteristic in a current path including this capacitor based on a predetermined arithmetic equation using a central processing unit (computer); displaying a frequency response graph on a screen of a display apparatus; having a designer evaluating the frequency response graph displayed on the display apparatus; and by determining an optimum capacitance value of the bypass capacitor by repeating this operation until an operating frequency comes close to a resonant frequency fr. In other words, the literature discloses a method that derives an optimum capacitance value of a bypass capacitor by actually installing the capacitor and calculating the characteristic thereof. Patent Literature 1, however, does not disclose that the characteristic of a bypass capacitor is not effective, depending on resonance condition of a wiring pattern itself. Further, the technology disclosed in Patent Literature 1 has a disadvantage that a solution cannot be derived when the resonant frequency of the wiring pattern is lower than the resonant frequency of the capacitor.
Patent Literature 2 discloses a checking method comprising: calculating an inductance of a wire from printed board design data 103; calculating a capacitance between a power supply plane layer and a ground plane layer; and calculating relation between an impedance between a power supply pin and a ground pin of an IC and a frequency from a characteristic of a bypass capacitor, an inductance of each wire, and an electrostatic capacity between the plane layers. The checking method further comprises: calculating a required impedance at an operating frequency of the IC, and compares the aforementioned impedance and the required impedance to decide whether the bypass capacitor is valid or invalid. This method is effective in examining a bypass capacitor having a self resonant frequency not higher than that of the power feeding line. However, Patent Literature 2 does not disclose any decoupling technique for the case wherein a bypass capacitor has a self resonant frequency higher than that of the power feeding line.
Patent Literature 3 discloses a printed wiring board that reduces the number of electronic components for reducing EMI and simplifies a board design by forming a wiring pattern (bypass pattern) for an electrical AC connection between each of power supply planes so that the wiring patterns stride over a region corresponding to a position of a first power supply plane (VCC1) and a region corresponding to a position of a second power supply plane (VCC2), and a region corresponding to a position of the second power supply plane (VCC2) and a region corresponding to a position of a third power supply plane (VCC3) in a signal layer directly under a power supply layer. The technology suppresses EMI (Electro Magnetic Interference) by providing a floating wiring region in a slit between different power feeding lines, however, it does not contribute in any way to the high frequency decoupling technology.
Patent Literature 4 discloses a mounting structure in which three power supply layers formed on an upper surface of or inside a mount board, a common ground layer formed on a plane different from the three power supply layers of the mount board, a power supply line disposed outside the mount board, and an IC as an electronic part, to which power is supplied from the plurality of power supply layers, are provided, chip-type three-terminal capacitors are mounted on the upper surface of the mount board, input and output electrodes of each of the chip-type three-terminal capacitors are electrically connected to two power supply layers so as to be inserted into a power supply current path constituted by the three power supply layers and the power supply line and a ground electrode of each three-terminal capacitor is electrically connected to the common ground layer. Patent Literature 4 discloses a power feeding line structure in which three layers of power feeding lines are connected by three-terminal capacitors. However, wiring design is complicated, the characteristic of the power feeding line for frequency components of noise are not reflected, and the technology is limited in terms of suppressing high frequency noise.
Patent Literature 5 discloses a method, apparatus and program that perform noise analysis on a printed wiring board and capable of verifying design appropriateness regarding power supply noise suppression.
Patent Literature 6 discloses a power supply noise analysis method and system for a electronic circuit board, and program, that comprises:
calculating a reflection voltage of an LSI based on an impedance characteristic between a power supply and ground of the electronic circuit board and an impedance characteristic between a power supply and ground of an LSI mounted on the board,
calculating a power supply noise flowing from the LSI to the electronic circuit board,
calculating propagation of the power supply noise flowing from the LSI to the electronic circuit board,
analyzing the power supply noise of the entire electronic circuit board based on a superposition principle, and
deciding appropriateness.
Patent Literature 7 discloses a method and apparatus for reproducing a mechanism of power supply noise generation, making it possible to grasp power supply noise in a design stage of a printed circuit board, and for deriving an input impedance between a power supply and GND of an LSI, that calculate a power supply input impedance of an LSI from the number of output buffers of the LSI, an output impedance of the output buffer, a characteristic impedance of power supply/GND of each of an LSI terminal, a package, and a chip terminal part, a characteristic impedance of a signal, a characteristic impedance of a wiring connected to an LSI output terminal, and a damping resistance of an output signal.
Each of Patent Literatures 5, 6, and 7 discloses a technique for analyzing a power feeding line and a technology for deriving a target impedance. There is not disclosed an effect on decoupling given by a size of a power feeding line at a high frequency.
In Patent Literature 8, a region to which a resistance element can be added later is provided between power supply terminals of an LSI, and consequently a Q value of a power supply resonance (resonance of a power supply noise) caused by a capacity component inside the LSI and an inductance component that a package and a board have is lowered to suppress the power supply noise. Further, when an impedance characteristic in a low frequency band deteriorates due to addition of a resistance element, a capacitance element is added to a power supply circuit. Further, Patent Literature 8 discloses the structure of a printed wiring board power supply circuit designing apparatus that makes a decision based on a power supply noise, regarding insertion of a resistance element between the power supply terminals of the LSI and addition of a capacitance element in the PCB on which the LSI having the additional region for resistance element is mounted. It is a technology that reduces a resonance level by inserting a resistance element in a power feeding line. In Patent Literature 8, there is not disclosed any technology regarding decoupling at a high frequency caused by a size of a power feeding line, either.
[PTL 1]
Japanese Patent Kokai Publication No. JP2001-175702A
[PTL 2]
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[PTL 3]
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[PTL 4]
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[PTL 5]
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[PTL 6]
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[PTL 7]
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[PTL 8]
Japanese Patent Kokai Publication No. JP2010-287740A